□ Seoyoung Jang, a student in the integrated master’s and doctoral program (advisor: Professor Gain Kim) in the Department of Electrical Engineering and Computer Science at DGIST (President Kunwoo Lee), received the “Best Student Paper Award” for a paper presented at the 51st European Solid-State Electronics Research Conference (ESSERC 2025). The award was presented at ESSERC 2026, held in Mallorca, Spain, from September 7 to 10.
□ ESSERC is one of Europe’s leading international conferences in the field of semiconductor circuits. Past recipients of the award have been from leading universities and research institutions in Europe and North America, making this a particularly rare achievement for a researcher from an Asian university.
□ The award-winning paper addresses next-generation ultra-high-speed inter-chip interface technology required for AI data centers and high-performance computing (HPC) systems and is the result of an international joint research collaboration between DGIST and IBM Research Europe-Zurich that has continued since 2022.
□ Seoyoung Jang developed an ultra-high-speed wired transmitter for the fast and efficient transmission of large volumes of data in AI data centers and HPC systems. High-speed inter-chip interfaces face the technical challenge of simultaneously achieving high speed and energy efficiency, as higher transmission speeds lead to increased channel loss, circuit complexity, and power consumption.
□ To address this challenge, the research team applied a discrete multitone (DMT) approach that divides a single wide frequency band into 31 subchannels and flexibly allocates data and power according to the channel characteristics of each frequency band. The team integrated the key digital signal processing functions required to generate DMT signals and a high-speed data converter onto a single chip, implementing it as an operational ultra-high-speed transmitter.
□ Based on data and power allocation information determined by the characteristics of the transmission line, the research team integrated the key digital signal processing and high-speed data conversion functions required to generate DMT signals into the chip and verified real-time operation. The fabricated transmitter chip achieved a maximum data transmission rate of 76.2 Gb/s while consuming 144 mW of power, simultaneously achieving high transmission speed and energy efficiency. Through an actual chip implementation, this achievement demonstrates the potential of the DMT-based transmitter architecture to be extended to ultra-high-speed, low-power inter-chip interfaces for future AI data centers.
□ “I am very pleased that we were able to implement on an actual chip a transmitter technology designed to simultaneously achieve the high transmission speed and energy efficiency required for inter-chip interfaces in AI data centers, and that our work has received international recognition,” stated Seoyoung Jang. “Based on this achievement, I plan to expand my research into next-generation high-speed interface and interconnect (chip-to-chip connection) technologies capable of speeds of 200 gigabits per second (200 Gb/s) or higher.”
□ DGIST plans to continue expanding joint research with leading research institutions worldwide and strengthening research and talent development in next-generation high-speed interface semiconductors and inter-chip connection technologies required for AI data centers and high-performance computing.
